The present invention is directed to a data processing system in which a plurality of data terminal devices are in communication with a host processor and more particularly, to a priority interrupt controller for processing interrupting messages from the terminal devices in accordance with a predetermined priority level arrangement.
Present data processing systems have included a central or a host processor and a plurality of data handling peripheral devices which are connected to the host processor for the purpose of exchanging information with the host processor. Since each of the peripheral devices operates independently of each other, conflicts can arise between a plurality of peripheral devices in trying to gain access to the host processor. The most common solution to this problem is to assign a priority level of access to each of the peripheral devices in which a peripheral device having a higher priority level will always gain access to the host processor over a peripheral device having a lower priority level when both devices are trying to gain access to the host processor at the same time. Examples of this type of arrangement can be found in U.S. Pat. Nos. 4,056,847 and 4,034,349, which are representative of priority interrupt controllers employed in prior art processing systems. One disadvantage of the priority systems found in the prior art is that the priority levels thus assigned prevent any reassignment of the priority levels without a reconfiguration of the priority circuits. In those situations when priority levels are required to be changed several times throughout the day, the prior art priority controllers are incapable of meeting this requirement, especially where cost is a factor. It is therefore an object of the present invention to provide a low cost, priority interrupt controller which can select various priority level arrangements for a plurality of remote data terminal devices when accessing a host processor. It is a further object of this invention to provide a low cost, priority interrupt controller which will continuously seek the highest priority terminal device requesting access to the host processor during a processing operation.